Publications in international Journals
J17. V.I. Kelefouras, Keramidas Georgios, Voros Nikolaos, "Combining software cache partitioning and loop tiling for effective shared cache management", has been accepted in ACM Transactions on Embedded Computing Systems (TECS) (IF: 1.367) 2017 J16. V.I.Kelefouras, "A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details", Journal of Computing, Springer (IF: 0.872) 2016 J15. V.I. Kelefouras, A. Kritikakou, I. Mporas and V. Kolonias, “A high performance Matrix-Matrix Multiplication methodology for CPU and GPU architectures”, Journal of Supercomputing, Springer (IF: 1.088) MMM.pdf J14. A.Kritikakou, F. Catthoor, V. Kelefouras and C. Goutis, “Array Size Computation under Uniform Overlapping & Irregular Accesses” ACM Transactions on Design Automation of Electronic Systems (TODAES) (IF: 0.52)
2015 J12. V.I. Kelefouras, Elissavet Papadima, A. S. Kritikakou and C.E. Goutis, «A Matrix Vector Multiplication Methodology for single/multi-core architectures», Journal of Supercomputing, Springer (IF: 1.088) MVM.pdf J11. V.I. Kelefouras, A.Kritikakou and C. Goutis, « A methodology of speeding up loop kernels by exploiting the software information and the memory architecture», Journal of Computer Languages, Systems & Structures (COMLAN), Elsevier, to appear, 2015 (IF: 0.458) compiler.pdf 2014 J10. V.I. Kelefouras, A. Kritikakou and C. Goutis «A Matrix Matrix Multiplication Methodology for Single/Multi-core architectures using SIMD», Journal of Supercomputing, Springer, Vol. 68, No. 3, pp. 1418-1440, Jan., 2014 (IF: 0.917) J9. V.I. Kelefouras, A. Kritikakou and C. Goutis «A Methodology for Speeding Up Edge and Line Detection Algorithms focusing on Memory Architecture Utilization», Journal of Supercomputing, Springer, Vol. 68, No. 1, pp. 459-487, Dec. 2013, DOI:10.1007/s11227-013-1049-x, (IF: 0.917) Canny.pdf J8. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «Near-optimal & Scalable Representation of Access Schemes for Memory Management», ACM Transaction on Architecture and code Optimization (TACO), Vol. 11, No.1, Feb., 2014 (IF: 0.824) 2013 J7. V.I. Kelefouras, A.Kritikakou, Konstantinos Siourounis and C. Goutis, “A methodology for speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices”, Journal of Signal Processing Systems, Springer, Vol. 77, No. 3, pp. 1-15 , 2013, DOI:10.1007/s11265-013-0812-9 (IF: 0.551) toeplitz.pdf J6. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «Near-optimal & Scalable Intra-signal In-place for Non-overlapping & Irregular Access Schemes», ACM Transaction on Design Automation of Electronic Systems, Vol.19, no. 1, Dec., 2013, DOI:10.1145/2534383 (IF: 0.685) J5. A.Kritikakou, F. Catthoor, G.S. Athanasiou, V.I. Kelefouras and C. Goutis, “Near-optimal Microprocessor & Accelerators Co-Design with Latency & Throughput Constraints”, ACM Trans. Architecture and Code Optimization, May, Vol. 10, No. 2, 2013, DOI:10.1145/2459316.2459317 (IF: 0.824) J4. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, “A systematic approach to classify design-time global scheduling techniques”, Journal of ACM Computed Surveys, Vol. 45, No. 2, Feb. 2013, DOI: 10.1145/2431211.2431213 (IF: 9.169) 2012 J3. N. Alachiotis, V.I. Kelefouras, G. Athanasiou, H. Michail, A. Kritikakou and C. Goutis, “A Data Locality Methodology for Matrix-MatrixMultiplication Algorithm”, Journal of Supercomputing, Springer, 2012, Vol. 59, No. 2, pp. 830--851, DOI: 10.1007/s11227-010-0474-3 (IF:0.917) J2. H.E. Michail, G.S. Athanasiou, V.I. Kelefouras, G. Theodoridis, C.E. Goutis, “On the exploitation of a high-throughput SHA-256 FPGA design for HMAC”, accepted for publishing in journal of ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 5, Iss. 1, March 2012. 2011 J1. V.I. Kelefouras, G.S. Athanasiou, N. Alachiotis, H. E. Michail, A. S. Kritikakou and C.E. Goutis, “A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization”, IEEE Transactions on Signal Processing, 2011, Vol.59, No 12, pp.6217-6226, DOI:10.1109/TSP.2011.2168525 (IF:2.829) FFT.pdf Publications in international Conferences 2018
B9. V.I. Kelefouras, Karim Djemame “Workflow Simulation Aware and Multi-Threading Effective Task Scheduling for Heterogeneous Computing”, 25th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC), 17-20 December 2018, Bengaluru, India B8. V.I. Kelefouras, Karim Djemame “A methodology for efficient code optimizations and memory management”, ACM International Conference on Computing Frontiers 2018 (CF '18), Ischia, Italy 2017
2015 B6. B A.Emeretlis, V. Kelefouras, G. Theodoridis, , M. Nanou, C.(T.) Politi, K. Georgoulakis, and G.O. Glentis, “FPGA IMPLEMENTATION OF A MIMO DFE IN 40 GB/S DQPSK OPTICAL LINKS”, has been accepted to EUSIPCO 2015, NICE, FRANCE. B5. A.Kritikakou, F. Catthoor, V.I. Kelefouras and C. Goutis, «Near-optimal & Scalable Representation of Access Schemes for Memory Management», Presentation at the Conference of European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), Amsterdam, The Netherlands, Jan., 2015 2014 B4. Andreas Emeretlis, V. I. Kelefouras, George Theodoridis, George - Othon Glentis, “EFFICIENT FPGA IMPLEMENTATIONS OF VOLTERRA DFES FOR OPTICAL SYSTEMS”, 2014 IEEE Dallas Circuits and Systems Conference (DCAS), Oct 12-13, 2014 2012 B3. Kritikakou, F.Catthoor, G.S. Athanasiou, V.I. Kelefouras and C. Goutis, “A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design”, Proc. Int’l Conf. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 16-19 July 2012 2010 2009 B1. H.E. Michail, D.A. Apostolopoulou, L.A. Anastasiou, V.K. Porpodas, G.S. Athanasiou, V.I. Kelefouras and C.E. Goutis, “Novel Hardware Implementation of the Cipher Message Authentication Code (CMAC)”, Oral Presentation in 1st Panhellenic Conference on Electronics and Telecommunications (PACET '08), Patras, Greece, 20-22 March 2009 Book Chapters C1. K. Djemame, R. Kavanagh, V. Kelefouras, A. Aguila, J. Ejarque, R.M. Badia, D. Garcia Perez, C. Pezuela, J-C. Deprez, L. Guedria, R. De Landtsheer and Y. Georgiou, “Towards an Energy-aware Framework for application development and execution in Heterogeneous parallel architectures” In: Accelerators for energy efficient data centers, C. Kachris (Ed.), 2018, pp. 175-196. C2. H.E. Michail, A.Gregoriades, G.S. Athanasiou, V.I. Kelefouras and C.E. Goutis, “Authentication with RIPEMD-160 and other alternatives: A Hardware Design Perspective”, accepted for publishing in the book "Advanced Technologies", ISBN 978-953-7619-X-X, 2010 |